Leakage Current Research Articles

Recess-free thin-barrier AlGaN/GaN Schottky barrier diodes with ultra-low leakage current: Experiment and simulation study

Recess-free thin-barrier AlGaN/GaN Schottky barrier diodes with ultra-low leakage current: Experiment and simulation study

Data-driven optimization for microgrid control under distributed energy resource variability

The integration of renewable energy resources into the smart grids improves the system resilience, provide sustainable demand-generation balance, and produces clean electricity with minimal leakage currents. However, the renewable sources are intermittent in nature. Therefore, it is necessary to develop scheduling strategy to optimise hybrid PV-wind-controllable distributed generator based Microgrids in grid-connected and stand-alone modes of operation. In this manuscript, a priority-based cost optimization function is developed to show the relative significance of one cost component over another for the optimal operation of the Microgrid. The uncertainties associated with various intermittent parameters in Microgrid have also been introduced in the proposed scheduling methodology. The objective function includes the operating cost of CDGs, the emission cost associated with CDGs, the battery cost, the cost of grid energy exchange, and the cost associated with load shedding. A penalty function is also incorporated in the cost function for violations of any constraints. Multiple scenarios are generated using Monte Carlo simulation to model uncertain parameters of Microgrid (MG). These scenarios consist of the worst as well as the best possible cases, reflecting the microgrid’s real-time operation. Furthermore, these scenarios are reduced by using a k-means clustering algorithm. The reduced procedures for uncertain parameters will be used to obtain the minimum cost of MG with the help of an optimisation algorithm. In this work, a meta-heuristic approach, grey wolf optimisation (GWO), is used to minimize the developed cost optimisation function of MG. The standard LV Microgrid CIGRE test network is used to validate the proposed methodology. Results are obtained for different cases by considering different priorities to the sub-objectives using GWO algorithm. The obtained results are compared with the results of Jaya and PSO (particle swarm optimization) algorithms to validate the efficacy of the GWO method for the proposed optimization problem.

Quantum‐Dots Matrix Encapsulated CsPbI3 Polycrystal Composite Films for Efficient and Bright Deep‐Red Light‐Emitting Diodes

AbstractAll‐inorganic CsPbI3 perovskite is a promising emitter for deep‐red light‐emitting diodes (LEDs). However, presently fabricated CsPbI3 polycrystalline films are composed of island‐like polycrystals, encountering the problems of serious interface current leakage and low‐efficiency carrier radiative recombination. Here, a CsPbI3‐xBrx quantum dots (QDs) matrix encapsulated CsPbI3 polycrystal film is reported to address the low‐efficiency issue of island‐like CsPbI3 polycrystalline film applied in deep‐red LEDs. The developed QDs matrix encapsulation strategy has two benefits. One is the filling of void space in the island‐like CsPbI3 polycrystal film to suppress the interface current leakage. The other more important benefit is utilizing the strong carrier confinement effect of QDs to strengthen the formation of excitons in the composite film and thus improve the electroluminescence efficiency. Moreover, interesting grain growth is found between CsPbI3‐xBrx QDs and CsPbI3 polycrystals, which further enhances the exciton transfer effect brought by the QDs matrix and optoelectronic properties of the fabricated composite films. Based on the obtained high‐quality QDs/polycrystal composite films, efficient and bright deep‐red LEDs are achieved with a peak external quantum efficiency of 15.24% and a maximum luminance of 3691 cd m−2.

Low temperature crystallization of atomic-layer-deposited SrTiO3 films with an extremely low equivalent oxide thickness of sub-0.4 nm

Despite SrTiO3(STO) possessing a high dielectric constant, its application as a capacitor dielectric in dynamic random-access memory(DRAM) capacitors faces challenges due to the high-temperature annealing for crystallization, its compositional inhomogeneity, and the high leakage currents of STO films. To address these issues, we employ atomic layer deposition(ALD) of STO films onto Pt substrates at elevated temperatures(340–380 °C). The use of low-reactivity Pt electrodes effectively mitigates the initial growth of excess Sr, ensuring enhanced compositional uniformity along the film growth direction. Coupled with ALD at high temperatures, this approach facilitates the crystallization of STO films in the as-grown state, further enhancing the crystallinity with increasing film thickness. Subsequent low-temperature post-deposition annealing (PDA) at 400 and 500 °C achieves full crystallization. This process results in a remarkable increase in the dielectric constant, reaching approximately 150. Furthermore, the absence of microcracks after PDA, attributed to the formation of adequately dense films, contributes to substantially improved dielectric properties. Consequently, these STO films exhibit an exceptionally low equivalent oxide thickness of 0.34 nm coupled with an ultralow leakage current of 3.7 × 10−8 A/cm2 at an operation voltage of 0.8 V, promising for advancing DRAM capacitors. This study presents a pathway for the sustainable scaling of DRAMs, addressing challenges in ALD-grown STO films.

Van der Waals Epitaxial Growth of Ultrathin Indium Antimonide on Arbitrary Substrates Through Low-thermal Budget.

III-V semiconductors possess high mobility, high frequency response, and detection sensitivity, making them potentially attractive for beyond-silicon electronics applications. However, the traditional heteroepitaxy of III-V semiconductors is impeded by a significant lattice mismatch and the necessity for extreme vacuum and high temperature conditions due to the low saturated vapor pressures of their constituent metals, thereby impeding their in situ compatibility with flexible substrates and silicon-based circuits. In this study, we present a novel approach to fabricate ultrathin InSb single-crystal nanosheets on arbitrary substrates with a thickness as thin as 2.4nm using low-thermal-budget Van der Waals (vdW) epitaxy through chemical vapor deposition (CVD). In particular, we have successfully achieved in-situ growth on both silicon-based substrates and flexible polyimide substrates. Notably, the growth temperature required for InSb nanosheets (240°C) is significantly lower than that employed in back-end-of-line processes (400°C). The field effect transistor (FET) devices based on fabricated ultrathin InSb nanosheets exhibit ultra-high On-off ratio exceeding 108 and demonstrate minimal gate leakage currents. Furthermore, these ultrathin InSb nanosheet display p-type characteristics with hole mobilities reaching up to 203 cm2v-1s-1 at room temperatures. This study paves the way for achieving heterogeneous integration of III-V semiconductors, ensuring compatibility with existing integrated circuit architecture and facilitating their application in flexible electronics, thereby realizing the potential of III-V nanometer-scale logic transistors. This article is protected by copyright. All rights reserved.

Capacitorless Two‐Transistor Dynamic Random‐Access Memory Cells Comprising Amorphous Indium–Tin–Gallium–Zinc Oxide Thin‐Film Transistors for the Multiply–Accumulate Operation

AbstractCapacitorless two‐transistor (2T0C) dynamic random‐access memory (DRAM) cells comprising oxide thin‐film transistors (TFTs) show potential as low‐power and high‐density DRAM cells; however, the multiply–accumulate (MAC) operation using these cells is not yet realized. In this study, 2T0C DRAM cells comprising amorphous indium–tin–gallium–zinc oxide TFTs are fabricated for MAC operations. In a 2T0C DRAM cell, one transistor acts as a write transistor and the other as a read transistor, whose gate capacitance corresponds to the data storage capacitance. The cells have a long retention time of 1000 s, which is 104 times longer than that of conventional DRAM cells, owing to the extremely low leakage current of the TFTs (1.11 × 10−18 A µm−1). These cells satisfy the original condition for synaptic devices, in which a proportional relationship exists between the input and output. The MAC operation is performed using two cells. This study demonstrates the usefulness of oxide TFTs in artificial neural networks.

Influence mechanism of Ni2O3 doping on leakage current of SnO2 varistor ceramics

AbstractThe doping of Ni2O3 has significantly enhanced the electrical properties and density of SnO2–Co3O4–Cr2O3–Nb2O5 varistor ceramics. The leakage current density is reduced to 4.73 µA/cm2, the nonlinear coefficient is 37, and the voltage gradient is 549 V/mm. The undoped varistor ceramics exhibited a considerably higher leakage current of 48.04 µA/cm2. The performance improvement comes from alterations in grain boundary parameters. The doping of an appropriate amount of Ni improves the grain boundary barrier of SnO2 varistor ceramics and makes samples obtain higher grain boundary resistance, which hinders the leakage current path and results in excellent nonohmic characteristics. The stable grain boundary barrier structure dominated by Ni enables the sample to obtain stable power loss performance under long‐term direct current (DC) bias.

Domain wall current, ferroelectric, and piezoelectric properties of flexible SrBi2Ta2O9 thin films affected by the distribution of a-oriented domains and c-oriented domains

We investigated the ferroelectric, piezoelectric, and domain wall current properties affected by the distribution of a-oriented domains and c-oriented domains in flexible SrBi2Ta2O9 (SBT) thin films on flexible Pt/mica substrates. On the flexible Pt/mica substrates, the SBT thin films with a mixed crystallinity of a-oriented and c-oriented crystallinities exhibited the domain structures mixed with a-oriented domains and c-oriented domains. The SBT thin films with excellent a-oriented crystallinity showed improved ferroelectric and piezoelectric properties due to the polar axis perpendicular to the c-axis. In particular, 90o domain walls composed of a-domain and c-domain have larger domain wall currents than 180o domain walls composed of c-domains, which increases the leakage current of the SBT thin films.

Grounding Fault Diagnosis of Running Rails Based on a Multi-scale One-Dimensional Convolutional Neural Network in a DC Subway System

AbstractRunning rails are the return conductors of the traction current in DC subway systems, which should be insulated from the earth. Due to the large length of the line, as well as the humidity and metal dust in the tunnel, grounding fault of the running rails usually occurs, which will increase stray current (SC) leakage and endanger power supply safety. In this paper, a method of grounding fault diagnosis of running rails based on a multi-scale one-dimensional convolutional neural network (MS-1DCNN) is proposed. Firstly, a platform for the dynamic distribution of SC and rail potential (RP) with grounding faults existing in the running rails is established, which generates the dynamic RP data with various grounding faults. Secondly, a grounding fault diagnostic method of running rails based on MS-1DCNN is proposed, so as to realize the effective identification of ground fault types in subway systems. Thirdly, with the proposed diagnostic method, the datasets under two operating conditions of a single train and two trains are tested; a comparison test between MS-1DCNN and the 1D convolutional neural network (1DCNN) is carried out, and the effectiveness of the proposed method is verified. Results demonstrate that the proposed model can significantly improve the ground fault diagnostic accuracy of running rails. The dynamic RP simulation platform for trains established in this paper lays a theoretical foundation for the grounding fault research of running rail. Moreover, the deep learning method is proposed for the first time to diagnose the grounding fault of running rail, and the high diagnostic accuracy is obtained, which is of great significance for the safe and stable operation of the subway line.

Van der Waals Epitaxially Grown Molecular Crystal Dielectric Sb2O3 for 2D Electronics.

Two-dimensional (2D) semiconducting materials have attracted significant interest as promising candidates for channel materials owing to their high mobility and gate tunability at atomic-layer thickness. However, the development of 2D electronics is impeded due to the difficulty in formation of high-quality dielectrics with a clean and nondestructive interface. Here, we report the direct van der Waals epitaxial growth of a molecular crystal dielectric, Sb2O3, on 2D materials by physical vapor deposition. The grown Sb2O3 nanosheets showed epitaxial relations of 0 and 180° with the 2D template, maintaining high crystallinity and an ultrasharp vdW interface with the 2D materials. As a result, the Sb2O3 nanosheets exhibited a high breakdown field of 18.6 MV/cm for 2L Sb2O3 with a thickness of 1.3 nm and a very low leakage current of 2.47 × 10-7 A/cm2 for 3L Sb2O3 with a thickness of 1.96 nm. We also observed two types of grain boundaries (GBs) with misorientation angles of 0 and 60°. The 0°-GB with a well-stitched boundary showed higher electrical and thermal stabilities than those of the 60°-GB with a disordered boundary. Our work demonstrates a method to epitaxially grow molecular crystal dielectrics on 2D materials without causing any damage, a requirement for high-performance 2D electronics.

First integration of Ni barrier layer for enhanced threshold switching characteristics in Ag/HfO2-based TS device

Utilizing Ag/HfO2 with nickel (Ni) as a barrier layer, a novel threshold switching (TS) device is devised to overcome challenges such as low reliability, high threshold voltage, and high leakage current. Compared against an Ag/Ti/HfO2-based TS device, the Ag/Ni/HfO2-based TS device exhibits improved electrical characteristics: yield enhancement from 31.7 % to 40.0 %, enhanced endurance from ∼10 cycles to ∼300 cycles, and suppression in off-state current (IOFF) from 1.2 × 10−7 A to 5.2 × 10−10 A under a high compliance current (e.g., 10−4 A). The results obtained through transmission electron microscopy (TEM), energy-dispersive X-ray spectroscopy (EDS), and atomic force microscopy (AFM) support the evidence of those accomplishments. Reducing the effective area of the TS device improves control over erratically generated filaments and the electric field within the switching layer, resulting in enhanced performance such as a reduced threshold voltage (VTH ∼0.35 V), minimized VTH variability (∼0.01 V), decreased a threshold current (ITH, i.e., the leakage current in the off-state before activation, ∼5.2 × 10−10 A), and maximum conductance (∼5.0 × 10−5 S) of low-resistance state. These findings suggest that the optimized Ag/Ni/HfO2-based TS device can serve as a practical solution for low-power applications.

Atom-Scaled Hafnium Doping for Strengthening the Germanium Oxide Interfacial Layer of The Gate Stack of Germanium P-Type Metal-Oxide-Semiconductor Field Effect Transistor

Abstract We have developed a method that uses a half-cycle Hf precursor adsorption to subtly dope GeO2 IL of the Hf-based gate stack through in situ plasma-enhanced atomic layer deposition. This technique can effectively reduce GeO vaporization and improve the thermal stability of the GeO2 layer. Our results indicated that the accumulation capacitance (Cacc) undergoing higher temperatures showed no noticeable increase in the capacitance-voltage (CV) curves once Hf was delicately introduced into the GeO2 layer. According to the Ge 3d spectra of X-ray photoelectron spectroscopy, we found that the IL had a signal from extra Hf-O bonds; thus, we conclude GeO evaporation can be suppressed substantially by Hf incorporation. As a result, adding metal into GeOx IL to form HfGeOx achieved a remarkably low leakage current of 9 × 10-5 A/cm2 and the lowest interface trap density (Dit) of approximately 2 × 1011 eV−1 cm−2 at 500C of PMA. In addition, applying this gate stack structure to device fabrication significantly reduced the leakage current of the off-state and improved the effective peak hole mobility.

Research on Leakage Current Waveform Spectrum Characteristics of Artificial Pollution Composite Insulator

In order to know about the change features of leakage current during the pollution flashover process of composite insulators, the study of the pollution flashover test on composite insulator under the pollutional condition is presented in the artificial fog cabinet. The characteristics of leakage current waveforms in time-domain and frequency-domain are measured and analyzed during the test. The analysis results show that there is a strong correlation among the fundamental harmonic, the third harmonic and fifth harmonic. The characteristics of leakage current spectrum are represented by the maximum value of leakage current (Im), total harmonic distortion (THD), and phase difference of fundamental leakage current (θ). During a near-flash event, the leakage current exhibits high amplitude, low harmonic content, and small phase difference between the fundamental leakage current and voltage. The research findings provide a basis for establishing a pollution flash warning system based on leakage current characteristic quantities.

Improved Common-Mode Leakage Current Measurement Method for Insulation Condition Monitoring in Distribution Grids

Common-mode (CM) leakage current is an essential insulation indicator for condition monitoring in distribution grids. However, online measurement of CM leakage current is a difficult task in the industry due to the disturbances of far larger load currents. To address this challenge, a novel CM leakage current measurement method based on multi-layer magnetic shield has been proposed in this paper. The analytical solution for the magnetic field around the shield is firstly derived and validated by finite element analysis. Comprehensive comparison with previous single-layer shield design is then conducted for a typical industrial case, proving that an improvement of about 46 dB can be achieved for CM leakage current measurement by the novel design. A sensor prototype has also been developed with optimized parameters and validated by experiments. The effectiveness of the proposed method is proved, with minor CM leakage current accurately extracted from load currents which are 3000 times larger.

Microstructure modification in Ba-doped SnO2-based ceramics with promising thermal conductivity and electrical properties

In this paper, the thermal conductivity of Ba-doped SnO2 varistors was tested using the heat flow method, and it was found that the thermal conductivity is related to the grain boundary barrier of the samples. Introducing the reduction of impurity phases and point defects is an effective method to enhance the thermal conductivity of SnO2-based varistors. Energy dispersive spectrograms indicate that the content of spinel Co2SnO4 doped with 1mol% Ba is the least when the arrester is operated at 40°C. The positive and negative charge defects are fully compensated, thereby reducing phonon scattering and improving the thermal conductivity of the samples. Spinel Co2SnO4 occupies the position of the effective grain boundary, so the reduction of Co2SnO4 and the compensation of positive and negative defects also effectively increase the grain boundary barrier. When the doping amount of Ba is 1mol%, the optimal potential barrier height is 1.48eV, the nonlinear coefficient is 45, the leakage current is 0.8μA/cm2 and the voltage gradient is 418V/mm.

Solution-processable low-voltage carbon nanotube field-effect transistors with high-k relaxor ferroelectric polymer gate insulator

Achieving energy-efficient and high-performance field-effect transistors (FETs) is one of the most important goals for future electronic devices. This paper reports semiconducting single-walled carbon nanotube FETs (s-SWNT-FETs) with an optimized high-k relaxor ferroelectric insulator P(VDF-TrFE-CFE) thickness for low-voltage operation. The s-SWNT-FETs with an optimized thickness (∼800 nm) of the high-k insulator exhibited the highest average mobility of 14.4 cm2 V−1s−1 at the drain voltage (I D) of 1 V, with a high current on/off ratio (I on/off >105). The optimized device performance resulted from the suppressed gate leakage current (I G) and a sufficiently large capacitance (>50 nF cm−2) of the insulating layer. Despite the extremely high capacitance (>100 nF cm−2) of the insulating layer, an insufficient thickness (<450 nm) induces a high I G, leading to reduced I D and mobility of s-SWNT-FETs. Conversely, an overly thick insulator (>1200 nm) cannot introduce sufficient capacitance, resulting in limited device performance. The large capacitance and sufficient breakdown voltage of the insulating layer with an appropriate thickness significantly improved p-type performance. However, a reduced n-type performance was observed owing to the increased electron trap density caused by fluorine proportional to the insulator thickness. Hence, precise control of the insulator thickness is crucial for achieving low-voltage operation with enhanced s-SWNT-FET performance.

Cylindrical hot cathode ionisation gauge – Construction and testing

Hot cathode ionisation gauges are indispensable in measuring high and ultra-high vacuum. In the present work the construction details and the metrological evaluation of a novel gauge design — the cylindrical ionisation gauge is presented. With the aim of enhancing accuracy and stability both in the short and long term, details of the mechanical assembling of electrodes and precautions to minimize leakage currents influencing ion current measurement are described. Performance evaluations demonstrate high short-term stability, with linearity error, reproducibility, and repeatability values consistently below 1 %, placing the gauge at the same level as the most stable ionisation gauges. Operating across a pressure range of at least 6 orders of magnitude, the gauge exhibits low linearity error from high to ultra-high vacuum ranges. Its capability to measure pressures below 10−9 mbar remains open and requires further investigation.

Role of tin clustering in band structure and thermodynamic stability of GeSn by atomistic modeling

Synthesis of device-quality GeSn materials with higher Sn compositions is hindered by various factors, such as Sn segregation, clustering, and short-range ordering effects. In the present work, the impact of the clustering of Sn atoms in a GeSn semiconductor alloy was studied by density functional theory using SG15 pseudopotentials in a Synopsys QuantumATK tool, where the thermodynamic stability, effective band structure, indirect and direct bandgaps, and density of states (DOS) were computed to highlight the difference between a cluster-free random GeSn alloy and a GeSn alloy with Sn–Sn clusters. A 54-atom bulk Ge1–xSnx (x = 3.71%–27.77%) supercell was constructed with cluster-free and a first nearest neighbor Sn–Sn clustered GeSn alloy at each composition for this work. Computation using the generalized gradient approximation exchange-correlation functional showed that the thermodynamic stability of GeSn was reduced due to the clustering of Sn, which increased the formation energy of the GeSn alloys by increasing the Hartree potential energy and exchange-correlation energy. Moreover, with the effective band structure of the GeSn material at a Sn composition of ∼22%, both direct (Eg,Γ) and indirect (Eg,L) bandgaps decreased by a large margin of 40.76 and 120.17 meV, respectively, due to Sn–Sn clustering. On the other hand, Eg,Γ and Eg,L decrease is limited to 0.5 and 12.8 meV, respectively, for Sn composition of ∼5.6%. Similar impacts were observed on DOS, in an independent computation without deducing from the electronic band structure, where the width of the forbidden band reduces due to the clustering of Sn atoms in GeSn. Moreover, using the energy bandgaps of GeSn computed with the assumption of it being a random alloy having well-dispersed Sn atoms needs revision by incorporating clustering to align with the experimentally determined bandgap. This necessitates incorporating the effect of Sn atoms clustered together at varying distributions based on experimental characterization techniques such as atom probe tomography or extended x-ray absorption fine structure to substantiate the energy bandgap of the GeSn alloy at a particular composition with precision. Hence, considering the effect of Sn clusters during material characterization, beginning with the accurate energy bandgap characterization of GeSn would help in mitigating the effect of process variations on the performance characteristics of GeSn-based group IV electronic and photonic devices such as varying leakage currents in transistors and photodiodes as well as the deviation from the targeted wavelength of operation in lasers and photodetectors.

Fully Symmetrical Hybrid PV Converter With Low Common-Mode Noise

Hybrid converters with multiports (simultaneous DC and AC outputs) are promising solutions to reduce conversion stages from solar energy to various loads, and thereby increasing the utilization of residential PV systems. Considering common-mode noises suppression and high reliability, this paper proposes a fully symmetrical hybrid PV converter concept with two DC ports and one AC port. The proposed converter adopts symmetrical boost impedances at the low-voltage DC port and symmetrical synchronization rectifier switches at the high-voltage DC port. In addition, a symmetrical AC-decoupling inverter, i.e., highly efficient and reliable inverter concept (HERIC), operates as either a boost switch or an inverter to perform DC-DC and DC-AC conversions simultaneously. Combined with a dedicated modulation method with deadtime, the proposed converter has low leakage currents for grid-connected PV applications, low CM noise as a DC-DC converter, and flexible power control capability. Experiments have been carried out on a prototype to verify the effectiveness of the proposed converter.

Zero-Resistance-Branch Electrical Drainage System to Solve the Adverse Influence of Stray Current on Buried Pipelines

The buried pipeline's ground potential may be seriously shifted by the stray current leaking from the rail transit, leading to the problem of severe electrochemical corrosion on buried pipeline. For this, a zero-resistance- branch electrical drainage system is proposed to solve the adverse influence of stray current on buried pipeline just like the APF technology in power systems, mainly consisting of a negative resistance compensating converter (NRCC) and a grounding electrode, which can directly drain the stray current to the soil without connecting the rail system. Moreover, the equivalent interference circuit model of stray current is established, and the corrosion rule is analyzed in detail. Furthermore, based on the NRCC, the zero-resistance active drainage control method is proposed to realize the absorption of stray current. As the optimization objective of the control method, the disturbance component of pipe-to-soil potential is regulated to be approximately 0, and the zero-resistance branch at the disturbance frequency can be realized without directly detecting the value of the stray current. Then, the stray current can be transferred to the new drainage branch to mitigate its electrochemical corrosion on buried pipelines. Finally, the experimental results verify the effectiveness of the proposed electrical drainage system.